The present invention is related to simulation of circuit designs, and more particularly to partial gate level simulations of a circuit design.
Electronic circuits are used in an enormously wide and important range of applications, such as computing, communications, control systems, etc. Common electronic circuits may include millions of transistors and are very difficult to design. Circuits are typically designed on computer systems using electronic design automation (EDA) software, combining logic gates and other circuit elements as needed to perform the desired function. Once a circuit has been designed, it typically undergoes a series of design verification steps such as a static timing analysis and gate level simulation before it is fabricated as a custom integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. Computerized design verification tools are used to simulate the circuit, exercising the clock and data inputs of a virtual representation of the circuit design and verifying that the circuit design performs correctly both at the outputs of the circuit and at selected internal nodes. Because of the enormous complexity of modern electronic circuits, the design verification step is often the most difficult and lengthy step in designing a circuit. Performing a full gate level simulation of a complex electronic circuit can require weeks to perform even on high performance computers, because each of the numerous logic gates in the circuit are tested in the simulation in various functional states.
The difficulty of designing complex electronic circuits is partially addressed by reusable circuit libraries called semiconductor intellectual property cores or IP cores, which contain reusable logic blocks that are designed to perform given functions and that can be included in a circuit design. Blocks from an IP core may be dropped into a circuit design to perform a desired function, rather than redesigning the circuitry to perform the function each time it is needed. IP cores are particularly important when designing a system on a chip (SOC), an electronic circuit such as a computer that performs multiple functions. For example, a computer may be designed as an SOC, using blocks from an IP core to provide a processor, memory, clock sources, external interfaces, power regulation, etc. IP cores may be supplied as generic gate netlists, a low level representation of the logic design, or as a synthesizable core having a higher abstraction level such as a hardware description language. Performing a gate level simulation of the circuit, including the blocks from the IP core, can take a great deal of computer processing time. The supplier of the IP core typically tests the design of the IP core, so the designer using the IP core may have the option of performing a gate level simulation only on circuitry outside the blocks from the IP core and forgoing gate level simulation of the blocks from the IP core. However, if a gate level simulation omits the blocks from the IP core, design flaws may go undetected because the interface between the blocks from the IP core and the remaining circuitry is not fully tested. The time required to perform a full gate level simulation of a complex electronic circuit takes on even more importance when considering the multiple iterations of a typical design process. The design verification in early stages of a design often identifies changes that must be made to the circuit design, requiring a modified circuit design which must then be reverified. Thus, the design process may require multiple full gate level simulations.
Existing methods exist for co-simulating mixed levels of abstraction for a circuit. These methods allow for timing gate simulations to be mixed with other simpler model abstractions (RTL, C etc.) These methods are deficient in that they do not specify a method that allows timing to be accurate across the boundary between the different abstractions of the circuit.
Thus, for at least the aforementioned reason, there exists a need in the art for a system for performing gate level simulations of a circuit design in a fast, efficient and effective manner, even when IP cores are used.